1. Field
The present invention relates to a power supply voltage adjusting device that adjusts the power supply voltage of a circuit depending on the process variance in the production process of a semiconductor integrated circuit such as a large scale integration (LSI) etc. and the temperature change during operation.
2. Description of the Related Art
With the widespread use of semiconductor integrated circuits of minimal dimensions in processing, process variances have caused signal delay time to each element and leakage current variances to each element. Therefore, when a predetermined power supply voltage is provided regardless of the variance of the element characteristic of a semiconductor integrated circuit, and if an element delay is shifted to a value larger than a designed value, then there are an increasing number of semiconductor integrated circuits that cannot satisfy a target operation frequency. If an element delay is shifted to a value smaller than a designed value, then a leakage current of an element is increased, thereby increasing the power consumption.
To reduce power consumption with high speed processing in solving the above-mentioned problems, Multi-Vth design is commonly used. In the Multi-Vth design, a plurality of cell libraries configured by transistors of different threshold voltages Vth are used.
For example, when two types of cell libraries, that is, a High-Vth transistor having a high Vth and a Low-Vth transistor having a low Vth, are used, a cell library configured by a High-Vth transistor operating with less leakage current at a low operation speed is used for a portion for which an adequate path delay time is allowed for a target operation frequency. On the other hand, a cell library configured by a Low-Vth transistor operating with more leakage current at a high operation speed is used for a portion for which there is no adequate path delay time allowed. Thus, the amount of leakage current passing through the entire circuit can be reduced.
Some techniques relating to adjustment of the power supply voltage of a circuit are proposed. One technique is that replica of a critical path is used to control a power supply voltage. The power supply control is performed depending on whether or not the delay of the critical path satisfies a target operation frequency based on the process variance.
Another technique is that a configuration in which, with a view to stably writing and erasing data for a non-volatile memory circuit, a first counter for counting the oscillation frequency of an internal oscillator and a second counter for counting a clock provided externally or a clock derived therefrom are provided and their count values are used so that a correct pulse width can be formed despite process variances for a write pulse and an erase pulse.
Another technique is that a circuit having a frequency generator for providing a clock signal having a frequency changing based in an operation voltage and a fixed frequency generator, also having a counter for counting the respective frequencies, thereby adjusting the power supply voltage by comparing the count values. It also discloses a configuration of adjusting a power supply voltage with the process variance taken into account by comparing the phase with a claim generated inside using a critical path network corresponding to the replica of a critical path.
However, in an LSI with a Multi-Vth design, the ratio between High-Vth cells and Low-Vth cells is different for each path, and each path has a different amount in change of allowed delay required to satisfy a target frequency for the operation condition such as a process variance, a power supply voltage, a temperature, etc. Therefore, there is more than one critical path to be considered in controlling the supply of the minimal voltage for an operation at a target frequency depending on the process variance.
For example, assume that there are a path A containing most of the cells as Low-Vth cells and a path B containing most of the cells as High-Vth cells, and there also are a first condition on which a delay of a High-Vth cell is shifted to a higher level and a delay of a Low-Vth cell is shifted to a higher level, and a second condition on which a delay of a High-Vth cell is shifted to a higher level and a delay of a Low-Vth cell is shifted to a lower level.
In this case, although the path A is a critical path in an LSI produced as biased on the first condition, there is the possibility that the path B is a critical path in an LSI produced as biased on the second condition.